1. Field of the Invention
The present invention relates to an apparatus for testing integrated circuits and a method thereof, and more specifically, to an apparatus for testing a bridge circuit and a method thereof.
2. Description of the Prior Art
Computers are widely used in all kinds of fields, and as the fabrication of semiconductors advances, CPU speeds are rapidly increasing. Besides the CPU, there are many other devices necessary for a computer to do various tasks. For example, a memory is used to store volatile data, a hard disk is used to store nonvolatile data, and a video card is used to drive display devices. In addition, there are also buses through which different devices in a computer can communicate. For example, a hard disk transmits/receives data to/from other devices in a computer via a PCI bus, a memory via a memory bus, a video card via an AGP bus, and a CPU via an FSB bus.
Different buses usually utilize different specifications, which are well known in the industry. Generally, different buses utilize different clock speeds, for example, in the prior art, the clock speed of a PCI bus is 33 MHz, that of an AGP bus is 66 MHz, that of a memory bus is 133 or 200 MHz, and that of a FSB bus is 266, 400, or 800 MHz. To communicate between different buses having different clock speeds, a bridge circuit (such as a “south bridge circuit” or a “north bridge circuit” in commonly used terminology) is needed. A bridge circuit is used to transfer data from one clock domain to another clock domain.
When a die is packaged (for example, a BGA package), the die must be tested according to a test vector to verify its function. However, since a bridge circuit is used to transfer data between different clock domains, a bridge circuit may be failed during testing due to the problem caused by different clock domains. This means that the result of the test procedure may be incorrect.
FIG. 1 is a timing diagram of a prior art bridge circuit. The drawing shows an example circuit in which a bridge circuit is used to transfer data from a higher clock domain (CLK1, 200 MHz, for example, a CPU controller) to a lower clock domain (CLK2, 133 MHz, for example, an AGP controller), and the ratio of CLK1 to CLK2 is 3:2. A prior art bridge circuit uses a flip-flop to store and output data. For example, the rising edge of CLK1 triggers a first flip-flop to sample the test data inputted by the CPU controller, and transfers the data to a second flip-flop; meanwhile, the falling edge of CLK2 triggers the second flip-flop to sample the test data outputted by the first flip-flop, which then outputs the test data.
A typical prior art test procedure utilizes the actual operation clocks (in this case, CLK1 and CLK2) of a bridge circuit to test it. In FIG. 1, at time T1, CLK1 generates a rising edge so that the first flip-flop of the bridge circuit samples the test data from the CPU controller. Then, at time T3, CLK2 generates a falling edge so that the second flip-flop of the bridge circuit samples the test data from the first flip-flop and then outputs the data. Please note that at time T5, CLK1 generates a rising edge so that the first flip-flop of the bridge circuit samples the test data from the CPU controller; however, next, at time T6 there is a falling edge of CLK2. The time interval between T5 and T6 may be too short for the first flip-flop to provide the second flip-flop with enough setup time. This means that the bridge circuit may not receive the correct test data in time, causing the test procedure to fail. Although during the test procedure the bridge circuit fails to transfer data from one clock domain to another clock domain at time T6, when the bridge circuit is in practical operation, the missed data will be re-transferred by the bridge circuit to complete the transmission. In short, even if a bridge circuit works normally in practical operation, it may fail the test procedure due to the problems caused by different clock domains.
The problem mentioned above also occurs when a bridge circuit transfers data from a lower clock domain (CLK2, 133 MHz, for example, an AGP controller) to a higher clock domain (CLK1, 200 MHz, for example, a CPU controller). In this case, the rising edge of CLK2 triggers a first flip-flop to sample the test data inputted by the AGP controller, and transfer the data to a second flip-flop; meanwhile, the falling edge of CLK1 triggers the second flip-flop to sample the test data outputted by the first flip-flop, and then output the test data to the CPU controller.
Please refer to FIG. 1. At time T1, CLK2 generates a rising edge so that the first flip-flop of the bridge circuit samples the test data from the AGP controller. Then, at time T2, CLK1 generates a falling edge so that the second flip-flop of the bridge circuit samples the test data stored in the first flip-flop and then outputs the test data. Please note that at time T4, when CLK1 and CLK2 respectively generate a falling edge and a rising edge at the same time, the second flip-flop may not be able to sample the test data successfully, and therefore, the test procedure may fail. Similarly, although during the test procedure the bridge circuit fails to transfer data from one clock domain to another clock domain at time T4, when the bridge circuit is in practical operation, the missed data will be re-transferred by the bridge circuit to complete the transmission. In short, even if a bridge circuit works normally in practical operation, it may still be failed during the test procedure due to the problems caused by different clock domains.